Benchmark circuits for clock scheduling and synthesis

10.4231/R7M32SSV

Cheng-Kok Koh , Chuan Yean Tan , Rickard F. Ewetz , Shankarshana Janarthanan

03/31/2017

This repository contains experimental data related to our ASP-DAC 2015, ISPD 2015, and DAC2015 publications.

benchmark testing clock synthesis clocks Complexity Theory design aids dynamic scheduling fast clock skew scheduling integrated circuits multi-corner multi-mode optimization skew time measurement timing Very Large Scale Integration (VLSI)