Subject
Creator
- Cheng-Kok Koh 3
- Darcy M. Bullock, 0000-0002-7365-1918 2
- Rickard F. Ewetz, 0000-0002-4183-6926 2
- Shankarshana Janarthanan 2
- Alexander M. Hainen 1
- Amanda Stevens 1
- Ananth V. Iyer 1
- Christopher Day 1
- Chuan Yean Tan 1
- Dutt J. Thakkar 1
Type
- Dataset 6
Date
subject: optimization type: dataset
Total is 6 Results
Link Pivot Algorithm for Offset Optimization
10.4231/R7GQ6VPT
Christopher Day, Darcy M. Bullock, 0000-0002-7365-1918
11/20/2014
This animation illustrates the use of the Link Pivot algorithm for optimizing offsets on a signalized arterial.
Civil Engineering Computer Science optimization traffic engineering traffic signal timing traffic signals
Benchmark circuits for clock scheduling and synthesis
10.4231/R7KH0K8Q
Cheng-Kok Koh, Rickard F Ewetz, 0000-0002-4183-6926
01/08/2015
This repository contains experimental data related to our ASP-DAC 2015 and ISPD 2015 publications.
benchmark testing clock synthesis clock trees clocks Complexity Theory design aids dynamic scheduling Electrical and Computer Engineering fast clock skew scheduling integrated circuits multi-corner multi-mode optimization skew time measurement timing VLSI
Sequence and Offset Optimization at a Diamond Interchange
10.4231/R7VD6WCH
Alexander M. Hainen, Amanda Stevens, Darcy M. Bullock, 0000-0002-7365-1918, Howell Li
03/10/2014
This video demonstrates the optimized performance at a diamond interchange at I-69 / 96th Street in northeast Indianapolis, IN.
Civil Engineering diamond interchange offset optimization sequence signal
Benchmark circuits for clock scheduling and synthesis
10.4231/R7M32SSV
Cheng-Kok Koh, Chuan Yean Tan, Rickard F. Ewetz, 0000-0002-4183-6926, Shankarshana Janarthanan
03/31/2017
This repository contains experimental data related to our ASP-DAC 2015, ISPD 2015, and DAC2015 publications.
benchmark testing clock synthesis clocks Complexity Theory design aids dynamic scheduling fast clock skew scheduling integrated circuits multi-corner multi-mode optimization skew time measurement timing Very Large Scale Integration (VLSI)
Benchmark circuits for clock scheduling and synthesis
10.4231/R7Q23X5D
Cheng-Kok Koh, Rickard F. Ewetz, 0000-0002-4183-6926, Shankarshana Janarthanan
03/26/2015
This repository contains experimental data related to our ASP-DAC 2015, ISPD 2015, and DAC2015 publications.
benchmark testing clock synthesis clock trees clocks Complexity Theory design aids dynamic scheduling Electrical and Computer Engineering fast clock skew scheduling integrated circuits multi-corner multi-mode optimization skew time measurement timing VLSI
Indiana’s Future Freight Traffic Optimization Model
10.4231/X1M2-TV82
Ananth V. Iyer, Dutt J. Thakkar, Janani Srinvasan, Saichandar Naini, Sanjayraj Mohanraj, Srinath Jayan, Steven Dunlop, Thomas Brady
08/18/2022
The results of this study indicate that systematic, model-based capacity planning analysis can be used effectively in planning transportation infrastructure improvements that are linked to specific industry clusters.
excel freight forecast freight logistics industry case study infrastructure planning management opensolver optimization ramp capacity
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Results 1 - 6 of 6