Creator
- Cheng-Kok Koh 3
- Rickard F. Ewetz, 0000-0002-4183-6926 2
- Shankarshana Janarthanan 2
- Chuan Yean Tan 1
- Rickard F Ewetz, 0000-0002-4183-6926 1
Type
- Dataset 3
Date
subject: optimization subject: clocks type: dataset
Total is 3 Results
Benchmark circuits for clock scheduling and synthesis
10.4231/R7M32SSV
Cheng-Kok Koh, Chuan Yean Tan, Rickard F. Ewetz, 0000-0002-4183-6926, Shankarshana Janarthanan
03/31/2017
This repository contains experimental data related to our ASP-DAC 2015, ISPD 2015, and DAC2015 publications.
benchmark testing clock synthesis clocks Complexity Theory design aids dynamic scheduling fast clock skew scheduling integrated circuits multi-corner multi-mode optimization skew time measurement timing Very Large Scale Integration (VLSI)
Benchmark circuits for clock scheduling and synthesis
10.4231/R7KH0K8Q
Cheng-Kok Koh, Rickard F Ewetz, 0000-0002-4183-6926
01/08/2015
This repository contains experimental data related to our ASP-DAC 2015 and ISPD 2015 publications.
benchmark testing clock synthesis clock trees clocks Complexity Theory design aids dynamic scheduling Electrical and Computer Engineering fast clock skew scheduling integrated circuits multi-corner multi-mode optimization skew time measurement timing VLSI
Benchmark circuits for clock scheduling and synthesis
10.4231/R7Q23X5D
Cheng-Kok Koh, Rickard F. Ewetz, 0000-0002-4183-6926, Shankarshana Janarthanan
03/26/2015
This repository contains experimental data related to our ASP-DAC 2015, ISPD 2015, and DAC2015 publications.
benchmark testing clock synthesis clock trees clocks Complexity Theory design aids dynamic scheduling Electrical and Computer Engineering fast clock skew scheduling integrated circuits multi-corner multi-mode optimization skew time measurement timing VLSI
Display #
Results 1 - 3 of 3